SH7709S Datasheet, PDF (753/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

CKIO
t_DRAKD
t_DRAKD
DRAK0/1
Figure 23.54 DRAK Output Timing
23.3.9 UDI-Related Pin Timing
Table 23.9 UDI-Related Pin Timing
VccQ = 3.3 ± 0.3V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3V, Ta = –20 to 75°C
Item
TCK cycle time
TCK high pulse width
TCK low pulse width
TCK rise/fall time
TRST setup time
TRST hold time
TDI setup time
TDI hold time
TMS setup time
TMS hold time
TDO delay time
ASEMD0 setup time
ASEMD0 hold time
Symbol
Min
Max Unit Figure
tTCKCYC
50
—
ns
23.55
tTCKH
12
—
ns
tTCKL
12
—
ns
tTCKf
—
4
ns
tTRSTS
12
—
ns
23.56
tTRSTH
50
—
tcyc
tTDIS
10
—
ns
23.57
tTDIH
10
—
ns
tTMSS
10
—
ns
tTMSH
10
—
ns
tTDOD
—
16
ns
tASEMDH
12
—
ns
23.58
tASEMDS
12
—
ns
1/2_VccQ
t_TCKCYC
t_TCKH
t_TCKL
V_IH V_IH
V_IL V_IL
V_IH
1/2_VccQ
t_TCKf
t_TCKf
Note: When clock is input from TCK pin
Figure 23.55 TCK Input Timing
Rev. 5.00, 09/03, page 709 of 760