SH7709S Datasheet, PDF (585/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

• Serial data transmission
Figure 16.6 shows a sample flowchart for serial transmission.
Use the following procedure for serial data transmission after enabling the SCIF for transmission.
1. SCIF status check and transmit data write:
Read serial status register (SCSSR) and check that the TDFE flag is set to 1, then write
transmit data to the transmit FIFO data register (SCFTDR), read 1 from the TDFE and TEND
flags, then clear these flags to 0.
The number of transmit data bytes that can be written is (16 - transmit trigger set number).
2. Serial transmission continuation procedure:
To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible,
then write data to SCFTDR, and then clear the TDFE flag to 0.
3. Break output at the end of serial transmission:
To output a break in serial transmission, set the port SC data register (SCPDR) and port SC
control register (SCPCR), then clear the TE bit to 0 in the serial control register (SCSCR). For
information on SCPDR and SCPCR, see section 16.2.8, Bit Rate Register (SCBRR).
In steps 1 and 2, it is possible to ascertain the number of data bytes that can be written from the
number of transmit data bytes in SCFTDR indicated by the upper 8 bits of the FIFO data count
register (SCFDR).
Rev. 5.00, 09/03, page 541 of 760