SH7709S Datasheet, PDF (37/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

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Burst ROM Bus Cycle (No Wait) ........................................................................ 678
Burst ROM Bus Cycle (Two Waits) .................................................................... 679
Burst ROM Bus Cycle (External Wait, WAITSEL = 1) ...................................... 680
Synchronous DRAM Read Bus Cycle (RCD = 0, CAS Latency = 1, TPC = 0) .. 681
Synchronous DRAM Read Bus Cycle (RCD = 2, CAS Latency = 2, TPC = 1) .. 682
Synchronous DRAM Read Bus Cycle (Burst Read (Single Read × 4),
RCD = 0, CAS Latency = 1, TPC = 1) ................................................................. 683
Synchronous DRAM Read Bus Cycle (Burst Read (Single Read × 4),
RCD = 1, CAS Latency = 3, TPC = 0) ................................................................. 684
Synchronous DRAM Write Bus Cycle (RCD = 0, TPC = 0, TRWL = 0)............ 685
Synchronous DRAM Write Bus Cycle (RCD = 2, TPC = 1, TRWL = 1)............ 686
Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write × 4),
RCD = 0, TPC = 1, TRWL = 0) ........................................................................... 687
Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write × 4),
RCD = 1, TPC = 0, TRWL = 0) ........................................................................... 688
Synchronous DRAM Burst Read Bus Cycle (RAS Down, Same Row
Address, CAS Latency = 1).................................................................................. 689
Synchronous DRAM Burst Read Bus Cycle (RAS Down, Same Row
Address, CAS Latency = 2).................................................................................. 690
Synchronous DRAM Burst Read Bus Cycle (RAS Down, Different Row
Address, TPC = 0, RCD = 0, CAS Latency = 1) .................................................. 691
Synchronous DRAM Burst Read Bus Cycle (RAS Down, Different Row
Address, TPC = 1, RCD = 0, CAS Latency = 1) .................................................. 692
Synchronous DRAM Burst Write Bus Cycle (RAS Down, Same Row
Address) ............................................................................................................... 693
Synchronous DRAM Burst Write Bus Cycle (RAS Down, Different Row
Address, TPC = 0, RCD = 0) ............................................................................... 694
Synchronous DRAM Burst Write Bus Cycle (RAS Down, Different Row
Address, TPC = 1, RCD = 1) ............................................................................... 695
Synchronous DRAM Auto-Refresh Timing (TRAS = 1, TPC = 1) ..................... 696
Synchronous DRAM Self-Refresh Cycle (TRAS = 1, TPC = 1) ......................... 697
Synchronous DRAM Mode Register Write Cycle ............................................... 698
PCMCIA Memory Bus Cycle (TED = 0, TEH = 0, No Wait) ............................. 699
PCMCIA Memory Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait,
WAITSEL = 1)..................................................................................................... 700
PCMCIA Memory Bus Cycle (Burst Read, TED = 0, TEH = 0, No Wait).......... 701
PCMCIA Memory Bus Cycle (Burst Read, TED = 1, TEH = 1, Two Waits,
Burst Pitch = 3, WAITSEL = 1)........................................................................... 702
PCMCIA I/O Bus Cycle (TED = 0, TEH = 0, No Wait)...................................... 703
PCMCIA I/O Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait,
WAITSEL = 1)..................................................................................................... 704
PCMCIA I/O Bus Cycle (TED = 1, TEH = 1, One Wait, Bus Sizing,
WAITSEL = 1)..................................................................................................... 705
Rev. 5.00, 09/03, page xxxvii of xliv