SH7709S Datasheet, PDF (644/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

19.8.2 Port G Data Register (PGDR)
Bit: 7
6
5
4
3
2
1
0
PG7DT PG6DT PG5DT PG4DT PG3DT PG2DT PG1DT PG0DT
Initial value: *
*
*
*
*
*
*
*
R/W: R
R
R
R
R
R
R
R
Note: * Undefined
The port G data register (PGDR) is an 8-bit read-only register that stores data for pins PTG7 to
PTG0. Bits PG7DT to PG0DT correspond to pins PTG7 to PTG0. When the function is general
input port, if the port is read the corresponding pin level is read. Table 19.14 shows the function of
PGDR.
PGDR is initialized by a power-on reset, after which the general input port function (pull-up MOS
on) is set as the initial pin function, and the corresponding pin levels are read.
Table 19.14 Port G Data Register (PGDR) Read/Write Operations
PGnMD1
0
1
PGnMD0
0
1
0
1
Pin State
Other function
(see table 18.1)
Reserved
Input (Pull-up
MOS on)
Input (Pull-up
MOS off)
Read
H'00
H'00
Pin state
Pin state
Write
Ignored (no effect on pin state)
Ignored (no effect on pin state)
Ignored (no effect on pin state)
Ignored (no effect on pin state)
(n = 0 to 7)
Rev. 5.00, 09/03, page 600 of 760