SH7709S Datasheet, PDF (177/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

6.3.3 Interrupt Control Register 1 (ICR1)
ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ0 to
IRQ5 individually: rising edge, falling edge, or low level. This register is initialized to H'4000 by a
power-on reset or manual reset, but is not initialized in standby mode.
Bit:
Initial value:
R/W:
15
MAI
0
R/W
14
13
12
11
10
9
8
IRQLVL BLMSK IRLSEN IRQ51S IRQ50S IRQ41S IRQ40S
1
0
0
0
0
0
0
R/W
R/W
RW
R/W
R/W
R/W
R/W
Bit: 7
6
5
4
3
2
1
0
IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit 15—Mask All Interrupts (MAI): When set to 1, all interrupt requests are masked while a
low level is being input to the NMI pin. Masks NMI interrupts in standby mode.
Bit 15: MAI
0
1
Description
All interrupt requests are not masked when NMI pin is low level
All interrupt requests are masked when NMI pin is low level
(Initial value)
Bit 14—Interrupt Request Level Detect (IRQLVL): Selects whether the IRQ3–IRQ0 pins are
used as four independent interrupt pins or as 15-level interrupt pins encoded as IRL3–IRL0.
Bit 14: IRQLVL Description
0
Used as four independent interrupt request pins IRQ3–IRQ0
1
Used as 15-level interrupt pins encoded as IRL3–IRL0
(Initial value)
Bit 13—BL Bit Mask (BLMSK): Specifies whether NMI interrupts are masked when the BL bit
in the SR register is 1.
Bit 13: BLMSK Description
0
NMI interrupts are masked when BL bit is 1
1
NMI interrupts are accepted regardless of BL bit setting
(Initial value)
Rev. 5.00, 09/03, page 133 of 760