SH7709S Datasheet, PDF (728/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Tr Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 (Tpc)
CKIO
tAD
A25 to A16
Row address
tAD tAD tAD
tAD tAD
A12 or A10
A15 to A0
CSn
Row
address
Row
address
tCSD3
Read command
tAD tAD
tAD
Column address (1-4)
tRWD
RD/WR
RAS
tRASD2
tRASD2
tCASD2
tCASD2
tAD
tCSD3
tRWD
CAS
DQMxx
tDQMD
D31 to D0
(read)
BS
tDQMD
tRDS2 tRDH2
tRDS2 tRDH2
tBSD
tBSD
CKE
DACKn
tDAKD1
(High)
tDAKD1
Figure 23.25 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read × 4), RCD = 1,
CAS Latency = 3, TPC = 0)
Rev. 5.00, 09/03, page 684 of 760