SH7709S Datasheet, PDF (426/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

CK
CMCNT0
input clock
CMCNT0
N
0
CMCOR0
N
Compare
match signal
CMF
CMI
Figure 11.27 CMF Setting Timing
Compare Match Flag Clearing Timing
The CMF bit in the CMCSR0 register is cleared by writing 0 to it after reading 1. Figure 11.28
shows the timing when the CMF bit is cleared by the CPU.
CMCSR0 write cycle
T₁
T₂
CK
CMF
Figure 11.28 Timing of CMF Clearing by the CPU
Rev. 5.00, 09/03, page 382 of 760