SH7709S Datasheet, PDF (199/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bits 3 and 2—Read/Write Select A (RWA1, RWA0): Selects the read cycle or write cycle as the
bus cycle of the channel A break condition.
Bit 3: RWA1
0
1
Bit 2: RWA0
0
1
0
1
Description
Condition comparison is not performed
(Initial value)
The break condition is the read cycle
The break condition is the write cycle
The break condition is the read cycle or write cycle
Bits 1 and 0—Operand Size Select A (SZA1, SZA0): Selects the operand size of the bus cycle
for the channel A break condition.
Bit 1: SZA1
0
1
Bit 0: SZA0
0
1
0
1
Description
The break condition does not include operand size
(Initial value)
The break condition is byte access
The break condition is word access
The break condition is longword access
Rev. 5.00, 09/03, page 155 of 760