SH7709S Datasheet, PDF (284/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit 2n + 1: AnSZ1 Bit 2n: AnSZ0
0
0
1
1
0
1
0
0
1
1
0
1
Port A / B
Not used
Used
Description
Reserved (Setting prohibited)
Byte (8-bit) size
Word (16-bit) size
Longword (32-bit) size
Reserved (Setting prohibited)
Byte (8-bit) size
Word (16-bit) size
Reserved (Setting prohibited)
10.2.3 Wait State Control Register 1 (WCR1)
Wait state control register 1 (WCR1) is a 16-bit readable/writable register that specifies the
number of idle (wait) state cycles inserted for each area. For some memories, data bus drive may
not be turned off quickly even when the read signal from the external device is turned off. This
can result in conflicts between data buses when consecutive memory accesses are to different
memories or when a write immediately follows a memory read. This LSI automatically inserts the
number of idle states set in WCR1 in those cases.
WCR1 is initialized to H'3FF3 by a power-on reset. It is not initialized by a manual reset or in
standby mode, and retains its contents.
Bit: 15
14
13
12
11
10
9
8
WAITSE — A6IW1 A6IW0 A5IW1 A5IW0 A4IW1 A4IW0
L
Initial value: 0
0
1
1
1
1
1
1
R/W: R/W
R
R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
A3IW1 A3IW0 A2IW1 A2IW0 —
Initial value: 1
1
1
1
0
R/W: R/W R/W R/W R/W
R
2
1
0
— A0IW1 A0IW0
0
1
1
R
R/W R/W
Rev. 5.00, 09/03, page 240 of 760