SH7709S Datasheet, PDF (697/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

22.4.3 UDI Reset
An UDI reset is executed by setting an UDI reset assert command in SDIR. An UDI reset is of the
same kind as a power-on reset. An UDI reset is released by inputting an UDI reset negate
command.
SDIR
UDI reset assert
UDI reset negate
Chip internal reset
CPU state
Branch to H'A0000000
Figure 22.3 UDI Reset
22.4.4 UDI Interrupt
The UDI interrupt function generates an interrupt by setting a command from the UDI in the
SDIR. An UDI interrupt is a general exception/interrupt operation, resulting in a branch to an
address based on the VBR value plus offset, and with return by the RTE instruction. This interrupt
request has a fixed priority level of 15.
UDI interrupts are not accepted in sleep mode or standby mode.
22.4.5 Bypass
The JTAG-based bypass mode for the UDI pins can be selected by setting a command from the
UDI in SDIR.
22.4.6 Using UDI to Recover from Sleep Mode
It is possible to recover from sleep mode by setting a command (0001) from the UDI in SDIR.
Rev. 5.00, 09/03, page 653 of 760