SH7709S Datasheet, PDF (75/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Addressing
Mode
PC-relative
Instruction
Format Effective Address Calculation Method
Rn
Effective address is sum of register PC and
Rn contents.
PC
+
PC + R0
Calculation Formula
PC + Rn
R0
Immediate
#imm:8
8-bit immediate data imm of TST, AND, OR, —
or XOR instruction is zero-extended.
#imm:8
8-bit immediate data imm of MOV, ADD, or —
CMP/EQ instruction is sign-extended.
#imm:8
8-bit immediate data imm of TRAPA
—
instruction is zero-extended and multiplied by
4.
Note:
For the addressing modes below that use a displacement (disp), the assembler descriptions
in this manual show the value before scaling (×1, ×2, or ×4) is performed according to the
operand size. This is done to clarify the operation of the IC. Refer to the relevant assembler
notation rules for the actual assembler descriptions.
@ (disp:4, Rn) ; Register indirect with displacement
@ (disp:8, Rn) ; GBR indirect with displacement
@ (disp:8, PC) ; PC-relative with displacement
disp:8, disp:12; PC-relative
Rev. 5.00, 09/03, page 31 of 760