SH7709S Datasheet, PDF (437/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bits 7 to 3—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 2—Counter Start 2 (STR2): Selects whether to run or halt timer counter 2 (TCNT2).
Bit 2: STR2
0
1
Description
TCNT2 count halted
TCNT2 counts
(Initial value)
Bit 1—Counter Start 1 (STR1): Selects whether to run or halt timer counter 1 (TCNT1).
Bit 1: STR1
0
1
Description
TCNT1 count halted
TCNT1 counts
(Initial value)
Bit 0—Counter Start 0 (STR0): Selects whether to run or halt timer counter 0 (TCNT0).
Bit 0: STR0
0
1
Description
TCNT0 count halted
TCNT0 counts
(Initial value)
12.2.3 Timer Control Registers (TCR)
The timer control registers (TCR) control the timer counters (TCNT) and interrupts. The TMU has
three TCR registers, one for each channel.
The TCR registers are 16-bit readable/writable registers that control the issuance of interrupts
when the flag indicating timer counter (TCNT) underflow has been set to 1, and also carry out
counter clock selection. When the external clock has been selected, they also select its edge.
Additionally, TCR2 controls the channel 2 input capture function and the issuance of interrupts
during input capture. The TCR registers are initialized to H'0000 by a power-on reset and manual
reset, but are not initialized in standby mode and retain their contents.
Rev. 5.00, 09/03, page 393 of 760