SH7709S Datasheet, PDF (169/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

6.2.6 Interrupt Exception Handling and Priority
Tables 6.4 and 6.5 list the codes for the interrupt event registers (INTEVT and INTEVT2), and the
order of interrupt priority. Each interrupt source is assigned a unique code. The start address of the
interrupt service routine is common to each interrupt source. This is why, for instance, the value of
INTEVT or INTEVT2 is used as offset at the start of the interrupt service routine and branched to
in order to identify the interrupt source.
The priority of the on-chip peripheral module, IRQ, and PINT interrupts is set within priority
levels 0–15 as required by using interrupt priority registers A–E (IPRA–IPRE). The priority of the
on-chip peripheral module, IRQ, and PINT interrupts is set to 0 by a reset.
When the priorities of multiple interrupt sources are set to the same level and such interrupts are
generated simultaneously, they are handled according to the default order shown in tables 6.4 and
6.5.
Rev. 5.00, 09/03, page 125 of 760