SH7709S Datasheet, PDF (380/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

11.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)
DMA channel control registers 0–3 (CHCR0–CHCR3) are 32-bit readable/writable registers that
specify the operation mode, transfer method, etc., for each channel.
Bit 20 is only used in CHCR3; it is not used in CHCR0 to CHCR2. Consequently, writing to this
bit is invalid in CHCR0 to CHCR2; 0 is read if this bit is read. Bit 19 is only used in CHCR2; it is
not used in CHCR0, CHCR1, and CHCR3. Consequently, writing to this bit is invalid in CHCR0,
CHCR1, and CHCR3; 0 is read if this bit is read. Bits 6 and 16 to 18 are only used in CHCR0 and
CHCR1; they are not used in CHCR2 and CHCR3. Consequently, writing to these bits is invalid
in CHCR2 and CHCR3; 0s are read if these bits are read.
These register values are initialized to 0 in a reset. The previous value is retained in standby mode.
Bit: 31
...
21
20
19
18
17
16
—
...
—
DI
RO
RL
AM
AL
Initial value: 0
...
0
0
0
0
0
0
R/W: R
...
R
(R/W)^*2 (R/W)^*2 (R/W)^*2 (R/W)^*2 (R/W)^*2
Bit: 15
14
13
12
11
10
9
8
DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
—
DS
TM
TS1 TS0
IE
TE
DE
Initial value: 0
0
0
0
0
0
0
0
R/W:
R
(R/W)^*2 R/W
R/W
R/W
R/W R/(W)^*1 R/W
Notes: 1. Only 0 can be written to the TE bit after 1 is read.
2. The DI, RO, RL, AM, AL, and DS bits are not included in some channels.
Rev. 5.00, 09/03, page 336 of 760