SH7709S Datasheet, PDF (632/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

19.2.2 Port A Data Register (PADR)
Bit:
Initial value:
R/W:
7
PA7DT
0
R/W
6
PA6DT
0
R/W
5
PA5DT
0
R/W
4
PA4DT
0
R/W
3
PA3DT
0
R/W
2
PA2DT
0
R/W
1
PA1DT
0
R/W
0
PA0DT
0
R/W
The port A data register (PADR) is an 8-bit readable/writable register that stores data for pins
PTA7 to PTA0. Bits PA7DT to PA0DT correspond to pins PTA7 to PTA0. When the pin function
is general output port, if the port is read the value of the corresponding PADR bit is returned
directly. When the function is general input port, if the port is read the corresponding pin level is
read. Table 19.2 shows the function of PADR.
PADR is initialized to H'00 by a power-on reset. It retains its previous value in standby mode and
sleep mode, and in a manual reset.
Table 19.2 Port A Data Register (PADR) Read/Write Operations
PAnMD1
0
1
PAnMD0
0
1
0
1
Pin State
Read
Write
Other function PADR value Value is written to PADR, but does not
(See table 18.1)
affect pin state
Output
PADR value Write value is output from pin
Input (Pull-up
MOS on)
Pin state
Value is written to PADR, but does not
affect pin state
Input (Pull-up
MOS off)
Pin state
Value is written to PADR, but does not
affect pin state
(n = 7 to 0)
Rev. 5.00, 09/03, page 588 of 760