SH7709S Datasheet, PDF (127/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

3.6.3 Usage Examples
Invalidating Specific Entries: Specific TLB entries can be invalidated by writing 0 to the entry’s
V bit. When the A bit is 1, the VPN and ASID specified by the write data is compared to the VPN
and ASID within the TLB entry selected by the entry address and data is written to the matching
way. If no match is found, there is no operation. R0 specifies the write data and R1 specifies the
address.
; R0=H'1547 381C R1=H'F201 3000
; MMUCR.IX=0
; VPN(31–17)=B'0001 0101 0100 011 VPN(11–10)=B'10 ASID=B'0001 1100
; corresponding entry association is made from the entry selected by
; the VPN(16–12)=B'1 0011 index, the V bit of the hit way is cleared to
; 0,achieving invalidation.
MOV.L R0,@R1
Reading the Data of a Specific Entry: This example reads the data section of a specific TLB
entry. The bit order indicated in the data field in figure 3.14 (2) is read. R0 specifies the address
and the data section of a selected entry is read to R1.
; R1=H'F300 4300
MOV.L @R0,R1
VPN(16-12)=B'00100
Way 3
3.7 Usage Note
The operations listed below must only be performed when the TLB is disabled or in the P1 or P2
area. Any subsequent operation that accesses the P0, P3, or U0 area must take place two or more
instructions after any of the below operations.
1. Change SR.MD or SR.BL
2. Execute the LDTLB instruction
3. Write to the memory-mapped TLB
4. Change MMUCR.
Rev. 5.00, 09/03, page 83 of 760