SH7709S Datasheet, PDF (213/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit 31—BRDR Valid Flag (DVF): Indicates whether a branch destination address is stored.
When a branch destination address is fetched, this flag is set to 1. This flag is set to 0 in reading
BRDR.
Bit 31: DVF
0
1
Description
The value of BRDR register is invalid
The value of BRDR register is valid
Bits 30 to 28—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 27 to 0—Branch Destination Address (BDA27 to BDA0): These bits store the first fetched
address after branch.
7.2.13 Break ASID Register A (BASRA)
Break ASID register A (BASRA) is an 8-bit read/write register that specifies the ASID that serves
as the break condition for channel A. It is not initialized by resets.
Bit: 7
BASA7
Initial value: *
R/W: R/W
Note: * Undefined value
6
BASA6
*
R/W
5
BASA5
*
R/W
4
BASA4
*
R/W
3
BASA3
*
R/W
2
BASA2
*
R/W
1
BASA1
*
R/W
0
BASA0
*
R/W
Bits 7 to 0—Break ASID A7 to 0 (BASA7 to BASA0): These bits store the ASID (bits 7 to 0)
that is the channel A break condition.
7.2.14 Break ASID Register B (BASRB)
Break ASID register B (BASRB) is an 8-bit read/write register that specifies the ASID that serves
as the break condition for channel B. It is not initialized by resets.
Bit: 7
BASB7
Initial value: *
R/W: R/W
Note: * Undefined value
6
BASB6
*
R/W
5
BASB5
*
R/W
4
BASB4
*
R/W
3
BASB3
*
R/W
2
BASB2
*
R/W
1
BASB1
*
R/W
0
BASB0
*
R/W
Bits 7 to 0—Break ASID A7 to 0 (BASB7 to BASB0): These bits store the ASID (bits 7 to 0)
that is the channel B break condition.
Rev. 5.00, 09/03, page 169 of 760