SH7709S Datasheet, PDF (562/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

16.2.4 Transmit FIFO Data Register (SCFTDR)
The transmit FIFO data register (SCFTDR) is a FIFO register comprising sixteen 8-bit stages that
stores data for serial transmission. When the SCIF detects that the transmit shift register (SCTSR)
is empty, it moves transmit data written in the SCFTDR into SCTSR and starts serial transmission.
Continuous serial transmission is performed until there is no transmit data left in SCFTDR. The
CPU can always write to SCFTDR.
When SCFTDR is full of transmit data (16 stages), no more data can be written. If writing of new
data is attempted, the data is ignored.
Bit: 7
6
5
4
3
2
1
0
R/W: W
W
W
W
W
W
W
W
16.2.5 Serial Mode Register (SCSMR)
The serial mode register (SCSMR) is an 8-bit register that specifies the SCIF serial
communication format and selects the clock source for the baud rate generator.
The CPU can always read and write to SCSMR. SCSMR is initialized to H'00 by a reset and in
standby or module standby mode.
Bit: 7
—
Initial value: 0
R/W: R
6
5
4
3
2
1
0
CHR
PE
O/E STOP
—
CKS1 CKS0
0
0
0
0
0
0
0
R/W R/W R/W R/W
R
R/W R/W
Bit 7—Reserved: This bit is always read as 0. The write value should always be 0.
Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data in asynchronous mode.
Bit 6: CHR
Description
0
8-bit data
1
7-bit data^*
(Initial value)
Note: * When 7-bit data is selected, the MSB (bit 7) of the transmit FIFO data register is not
transmitted.
Rev. 5.00, 09/03, page 518 of 760