SH7709S Datasheet, PDF (727/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

CKIO
A25 to A16
A12 or A10
A15 to A0
CSn
RD/WR
RAS
CAS
DQMxx
D31 to D0
BS
Tr
Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4
(Tpc) (Tpc)
tAD
Row address
tAD
tAD
tAD
tAD
Row
address
Read command
tAD
tAD
Read A
command
tAD
Row
address
tCSD3
Column address (1-4)
tAD
tCSD3
tRWD
tRWD
tRASD2 tRASD2
tCASD2
tDQMD
tRDS2 tRDH2
tCASD2
tDQMD
tRDS2 tRDH2
tBSD
tBSD
CKE
DACKn
tDAKD1
(High)
tDAKD1
Figure 23.24 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read × 4), RCD = 0,
CAS Latency = 1, TPC = 1)
Rev. 5.00, 09/03, page 683 of 760