SH7709S Datasheet, PDF (510/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Transmitting
station
Serial communication line
Receiving
station A
(ID = 01)
Receiving
station B
(ID = 02)
Receiving
station C
(ID = 03)
Receiving
station D
(ID = 04)
Serial
data
H'01
(MPB = 1)
H'AA
(MPB = 0)
ID transmit cycle:
specifies receiving station
MPB: Multiprocessor bit
Data transmit cycle:
data transmission to
receiving station specified
by ID
Figure 14.12 Communication Among Processors Using Multiprocessor Format
(Sending Data H'AA to Receiving Processor A)
Communication Formats: Four formats are available. Parity-bit settings are ignored when the
multiprocessor format is selected. For details see table 14.11.
Clock: See the description in the asynchronous mode section.
Transmitting Multiprocessor Serial Data: Figure 14.13 shows a sample flowchart for
transmitting multiprocessor serial data. The procedure for transmitting multiprocessor serial data
is:
1. SCI status check and transmit data write: Read the serial status register (SCSSR), check that
the TDRE bit is 1, then write transmit data in the transmit data register (SCTDR). Also set
MPBT (multiprocessor bit transfer) to 0 or 1 in SCSSR. Finally, clear TDRE to 0.
2. To continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if
it reads 1); if so, write data in SCTDR, then clear TDRE to 0.
3. To output a break at the end of serial transmission: Set the port SC data register (SCPDR) and
port SC control register (SCPCR), then clear the TE bit to 0 in the serial control register
(SCSCR). For SCPCR and SCPDR settings, see section 14.2.8, SC Port Control Register
(SCPCR)/SC Port Data Register (SCPDR).
Rev. 5.00, 09/03, page 466 of 760