SH7709S Datasheet, PDF (776/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

32-Bit Bus Width
Byte
Byte
Byte
Byte
Word Word
Pin
Access Access Access Access Access Access Longword
(Address (Address (Address (Address (Address (Address Access
4n)
4n + 1) 4n + 2) 4n + 3)
4n)
4n + 2)
CS6 to CS2, CS0
Enabled Enabled Enabled Enabled Enabled Enabled Enabled
RD
R Low
Low
Low
Low
Low
Low
Low
W—
—
—
—
—
—
—
RD/WR
R High
High
High
High
High
High
High
W—
—
—
—
—
—
—
BS
Enabled Enabled Enabled Enabled Enabled Enabled Enabled
RAS3U/PTE[2]
High
High
High
High
High
High
High
RAS3L/PTJ[0]
High
High
High
High
High
High
High
CASL/PTJ[2]
High
High
High
High
High
High
High
CASU/PTJ[3]
High
High
High
High
High
High
High
WE0/DQMLL
R High
High
High
High
High
High
High
W—
—
—
—
—
—
—
WE1/DQMLU/WE
R High
High
High
High
High
High
High
W—
—
—
—
—
—
—
WE2/DQMUL/
ICIORD/PTK[6]
R High
W—
High
—
High
—
High
—
High
—
High
—
High
—
WE3/DQMUU/
ICIOWR/PTK[7]
R High
W—
High
—
High
—
High
—
High
—
High
—
High
—
CE2A/PTE[4]
High
High
High
High
High
High
High
CE2B/PTE[5]
High
High
High
High
High
High
High
CKE/PTK[5]
WAIT
Disabled Disabled Disabled Disabled Disabled Disabled Disabled
Enabled^*1 Enabled^*1 Enabled^*1 Enabled^*1 Enabled^*1 Enabled^*1 Enabled^*1
IOIS16/PTG[7]
Disabled Disabled Disabled Disabled Disabled Disabled Disabled
A25 to A0
Address Address Address Address Address Address Address
D7 to D0
Invalid
data
Invalid
data
Invalid
data
Valid
data
Invalid
data
Valid
data
Valid
data
D15 to D8
Invalid
data
Invalid
data
Valid
data
Invalid
data
Invalid
data
Valid
data
Valid
data
D23 to D16
Invalid
data
Valid
data
Invalid
data
Invalid
data
Valid
data
Invalid
data
Valid
data
D31 to D24
Valid
data
Invalid
data
Invalid
data
Invalid
data
Valid
data
Invalid
data
Valid
data
Notes: 1. Disabled when WCR2 register wait setting is 0.
2. Unused data pins should be switched to the port function, or pulled up.
Rev. 5.00, 09/03, page 732 of 760