SH7709S Datasheet, PDF (464/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit 3—Alarm Interrupt Enable Flag (AIE): When the alarm flag (AF) is set to 1, the AIE bit
allows interrupts.
Bit 3: AIE
0
1
Description
An alarm interrupt is not generated when the AF flag is set to 1
(Initial value)
An alarm interrupt is generated when the AF flag is set to 1
Bit 0—Alarm Flag (AF): The AF flag is set to 1 when the alarm time set in an alarm register
(only registers with ENB bit set to 1) matches the clock and calendar time. This flag is cleared to
0 when 0 is written, but holds its previous value when 1 is written.
Bit 0: AF
Description
0
Clock/calendar and alarm register have not matched since last reset to 0
Clearing condition: When 0 is written to AF
(Initial value)
1
Setting condition: Clock/calendar and alarm register have matched (only
registers with ENB set)^*
Note: * Contents do not change when 1 is written to AF.
13.2.16 RTC Control Register 2 (RCR2)
The RTC control register 2 (RCR2) is an 8-bit readable/writable register for periodic interrupt
control, 30-second adjustment ADJ, divider circuit RESET, and RTC count start/stop control. It is
initialized to H'09 by a power-on reset. It is initialized except for RTCEN and START by a
manual reset. It is not initialized, and retains its contents, in standby mode.
Bit: 7
PEF
Initial value: 0
R/W: R/W
6
5
4
3
2
1
0
PES2 PES1 PES0 RTCEN ADJ RESET START
0
0
0
1
0
0
1
R/W R/W R/W R/W R/W R/W R/W
Bit 7—Periodic Interrupt Flag (PEF): Indicates interrupt generation with the period designated
by the PES bits. When set to 1, PEF generates periodic interrupts.
Bit 7: PEF
0
1
Description
Interrupts not generated with the period designated by the PES bits
Clearing condition: When 0 is written to PEF
(Initial value)
Interrupts generated with the period designated by the PES bits
Setting condition: When 1 is written to PEF
Rev. 5.00, 09/03, page 420 of 760