SH7709S Datasheet, PDF (203/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

7.2.7 Break Data Mask Register B (BDMRB)
BDMRB is a 32-bit read/write register. BDMRB specifies bits masked in the break data specified
by BDRB. A power-on reset initializes BDMRB to H'00000000.
Bit: 31
30
29
28
27
26
25
24
BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 23
22
21
20
19
18
17
16
BDMB23 BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15
14
13
12
11
10
9
8
BDMB15 BDMB14 BDMB13 BDMB12 BDMB11 BDMB10 BDMB9 BDMB8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
BDMB7 BDMB6 BDMB5 BDMB4 BDMB3 BDMB2 BDMB1 BDMB0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bits 31 to 0—Break Data Mask Register B31 to B0 (BDMB31 to BDMB0): Specifies bits in
the channel B break data bits specified by BDRB (BDB31—BDB0).
Bits 31 to 0:
BDMBn
Description
0
Break data BDBn of channel B is included in the break condition (Initial value)
1
Break data BDBn of channel B is masked and is not included in the break
condition
n = 31 to 0
Notes: 1. Specify an operand size when including the value of the data bus in the break condition.
2. When a byte size is specified as a break condition, the same-byte data must be set in
bits 15 to 8 and bits 7 to 0 in BDRB for the break data.
Rev. 5.00, 09/03, page 159 of 760