SH7709S Datasheet, PDF (69/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

2.2 Data Formats
2.2.1 Data Format in Registers
Register operands are always longwords (32 bits, figure 2.6). When a memory operand is only a
byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register.
31
0
Longword
Figure 2.6 Longword
2.2.2 Data Format in Memory
Memory data formats are classified into bytes, words, and longwords. Memory can be accessed in
8-bit byte, 16-bit word, or 32-bit longword form. A memory operand less than 32 bits in length is
sign-extended before being stored in a register.
A word operand must be accessed starting from a word boundary (even address of a 2-byte unit:
address 2n), and a longword operand starting from a longword boundary (even address of a 4-byte
unit: address 4n). An address error will result if this rule is not observed. A byte operand can be
accessed from any address.
Big-endian or little-endian byte order can be selected for the data format. The endian mode should
be set with the MD5 external pin in a power-on reset. Big-endian mode is selected when the MD5
pin is low, and little-endian when high. The endian mode cannot be changed dynamically. Bit
positions are numbered left to right from most-significant to least-significant. Thus, in a 32-bit
longword, the leftmost bit, bit 31, is the most significant bit and the rightmost bit, bit 0, is the least
significant bit.
The data format in memory is shown in figure 2.7.
Address A + 1 Address A + 3 Address A + 10 Address A + 8
Address A Address A + 2 Address A + 11 Address A + 9
31 23 15 7 0 31 23 15 7 0
Address A Byte0 Byte1 Byte2 Byte3 Byte3 Byte2 Byte1 Byte0
Address A + 4
Word0
Word1
Word1
Word0
Address A + 8
Longword
Longword
Address A + 8
Address A + 4
Address A
Big-endian mode
Little-endian mode
Figure 2.7 Data Format in Memory
Rev. 5.00, 09/03, page 25 of 760