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| SH7709S Datasheet, PDF (349/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series | |||
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CKIO
T1
TW
TW
TB2 TB1
TW
TB2 TB1
T2
A25 to A4
A3 to A0
CSn
RD/WR
RD
D31 to
D0
BS
WAIT
Note: For a write cycle, a basic bus cycle (write cycle) is performed.
Figure 10.29 Burst ROM Wait Access Timing
Rev. 5.00, 09/03, page 305 of 760
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