SH7709S Datasheet, PDF (534/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

15.1.2 Block Diagram
Figure 15.1 shows a block diagram of the smart card interface.
Module data bus
RxD
TxD
SCK
SCRDR
SCRSR
SCTDR
SCTSR
SCSCMR
SCSSR
SCSCR
SCSMR
Transmit/
receive
control
SCBRR
Baud rate
generator
Parity generation
Parity check
Clock
External clock
SCI
Legend
SCSCMR: Smart card mode register
SCRSR: Receive shift register
SCRDR: Receive data register
SCTSR: Transmit shift register
SCTDR: Transmit data register
SCSMR: Serial mode register
SCSCR: Serial control register
SCSSR: Serial status register
SCBRR: Bit rate register
Figure 15.1 Block Diagram of Smart Card Interface
Internal
data bus
Pφ
Pφ/4
Pφ/16
Pφ/64
TXI
RXI
ERI
Rev. 5.00, 09/03, page 490 of 760