SH7709S Datasheet, PDF (76/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

2.3.3 Instruction Formats
Table 2.3 explains the meaning of instruction formats and source and destination operands. The
meaning of the operands depends on the operation code. The following symbols are used.
xxxx: Operation code
mmmm: Source register
nnnn: Destination register
iiii:
Immediate data
dddd: Displacement
Table 2.3 Instruction Formats
Instruction Format
0 format 15
xxxx xxxx
n format 15
xxxx nnnn
0
xxxx xxxx
0
xxxx xxxx
m format 15
0
xxxx mmmm xxxx xxxx
Source
Operand
—
Destination
Operand
—
—
nnnn: register
direct
Control register or
system register
Control register or
system register
mmmm: register
direct
mmmm: register
indirect with post-
increment
mmmm: register
indirect
mmmm: PC-
relative using Rm
nnnn: register
direct
nnnn: register
indirect with
pre-decrement
Control register
or system
register
Control register
or system
register
—
—
Instruction
Example
NOP
MOVT Rn
STS
MACH,Rn
STC.L
SR,@–Rn
LDC
Rm,SR
LDC.L
@Rm+,SR
JMP @Rm
BRAF Rm
Rev. 5.00, 09/03, page 32 of 760