SH7709S Datasheet, PDF (269/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

10.1.2 Block Diagram
Figure 10.1 shows a block diagram of the bus state controller.
Bus
interface
WAIT
Wait
controller
WCR1
WCR2
CS0, CS6 to CS2,
CE2A, CE2B
MCS0 to MCS7
BS
RD
RD/WR
WE3 to WE0
RASxx
CASx
CKE
ICIORD, ICIOWR
IOIS16
Interrupt
controller
Area
controller
Memory
controller
Refresh
controller
BCR1
BCR2
MCR
PCR
MCSCRn
RFCR
RTCNT
Comparator
RTCOR
RTCSR
Legend
WCR: Wait state control register
BCR: Bus control register
MCR: Memory control register
PCR: PCMCIA control register
BSC
RFCR: Refresh count register
RTCNT: Refresh timer count register
RTCOR: Refresh time constant register
RTCSR: Refresh timer control/status register
MCSCRn: MCSn control register (n = 0−7)
Figure 10.1 Block Diagram of Bus State Controller
Rev. 5.00, 09/03, page 225 of 760