SH7709S Datasheet, PDF (580/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

16.2.10 FIFO Data Count Register (SCFDR)
SCFDR is a 16-bit register which indicates the quantity of data stored in the transmit FIFO data
register (SCFTDR) and the receive FIFO data register (SCFRDR). It indicates the quantity of
transmit data in SCFTDR with the upper 8 bits, and the quantity of receive data in SCFRDR with
the lower 8 bits. SCFDR can always be read by the CPU.
Upper 8 Bits: 15
14
13
12
11
10
9
8
—
—
—
T4
T3
T2
T1
T0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
The upper 8 bits of SCFDR indicate the quantity of non-transmitted data stored in SCFTDR. H'00
means no transmit data, and H'10 means that SCFTDR is full of transmit data.
Lower 8 Bits: 7
6
5
4
3
2
1
0
—
—
—
R4
R3
R2
R1
R0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
The lower 8 bits of SCFDR indicate the quantity of receive data stored in SCFRDR. H'00 means
no receive data, and H'10 means that SCFRDR full of receive data.
Rev. 5.00, 09/03, page 536 of 760