SH7709S Datasheet, PDF (408/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

• Burst Mode, Level Detection
In the case of burst mode with level detection, the DREQ sampling timing is the same as in
cycle-steal mode.
For example, in figure 11.20, DMAC transfer begins, at the earliest, three cycles after the first
sampling is performed. The second sampling is started two cycles after the first. Subsequent
sampling operations are performed in the idle cycle following the end of the DMA transfer
cycle.
In burst mode, also, the DACK output period is the same as in cycle-steal mode.
• Burst Mode, Edge Detection
In the case of burst mode with edge detection, DREQ sampling is only performed once.
For example, in figure 11.21, DMAC transfer begins, at the earliest, three cycles after the first
sampling is performed. After this, DMAC transfer is executed continuously until the number
of data transfers set in the DMATCR register have been completed. DREQ is not sampled
during this time.
To restart DMAC after it has been suspended by an NMI, first clear NMIF, then input an edge
request again.
In burst mode, also, the DACK output period is the same as in cycle-steal mode.
Rev. 5.00, 09/03, page 364 of 760