SH7709S Datasheet, PDF (67/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

2.1.3 System Registers
System registers can be accessed by the LDS and STS instructions. When an exception occurs, the
contents of the program counter (PC) are saved in the saved program counter (SPC). The SPC
contents are restored to the PC by the RTE instruction used at the end of the exception handling.
There are four system registers, as follows.
• Multiply and accumulate high register (MACH)
• Multiply and accumulate low register (MACL)
• Procedure register (PR)
• Program counter (PC)
The system register configuration is shown in figure 2.4.
31
MACH
MACL
31
PR
31
PC
System Registers
0
Multiply and Accumulate High and Low Registers
(MACH/L)
Store the results of multiply-and-accumulate operations.
0 _{Procedure Register (PR)}
Stores the return address for exiting a subroutine
procedure.
0
Program Counter (PC)
Indicates the address four addresses (two instructions)
ahead of the currently executing instruction. Initialized
to H'A0000000 by a reset.
Figure 2.4 System Registers
2.1.4 Control Registers
Control registers can be accessed in privileged mode using the LDC and STC instructions. The
GBR register can also be accessed in user mode. There are five control registers, as follows:
• Status register (SR)
• Saved status register (SSR)
• Saved program counter (SPC)
• Global base register (GBR)
• Vector base register (VBR)
Rev. 5.00, 09/03, page 23 of 760