SH7709S Datasheet, PDF (36/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

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Port H ................................................................................................................... 601
Port J .................................................................................................................... 603
Port K ................................................................................................................... 605
Port L.................................................................................................................... 607
SC Port ................................................................................................................. 609
Block Diagram of A/D Converter ........................................................................ 614
A/D Data Register Access Operation (Reading H'AA40) .................................... 622
Example of A/D Converter Operation (Single Mode, Channel 1 Selected) ......... 624
Example of A/D Converter Operation (Multi Mode, Channels AN0 to AN2
Selected)............................................................................................................... 626
Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2
Selected)............................................................................................................... 628
A/D Conversion Timing ....................................................................................... 629
External Trigger Input Timing ............................................................................. 630
Definitions of A/D Conversion Accuracy ............................................................ 632
Example of Analog Input Protection Circuit ........................................................ 633
Analog Input Pin Equivalent Circuit .................................................................... 633
Block Diagram of D/A Converter ........................................................................ 635
Example of D/A Converter Operation.................................................................. 639
Block Diagram of UDI ......................................................................................... 642
TAP Controller State Transitions ......................................................................... 651
UDI Reset............................................................................................................. 653
EXTAL Clock Input Timing ................................................................................ 665
CKIO Clock Input Timing ................................................................................... 665
CKIO Clock Output Timing................................................................................. 665
Power-on Oscillation Settling Time ..................................................................... 666
Oscillation Settling Time at Standby Return (Return by Reset)........................... 666
Oscillation Settling Time at Standby Return (Return by NMI)............................ 667
Oscillation Settling Time at Standby Return (Return by IRQ4 to IRQ0,
PINT0/1, IRL3 to IRL0)....................................................................................... 667
PLL Synchronization Settling Time during Standby Recovery (Reset or NMI) .. 668
PLL Synchronization Settling Time during Standby Recovery (IRQ/IRL or
PINT0/PINT1 Interrupt)....................................................................................... 668
PLL Synchronization Settling Time when Frequency Multiplication Rate
Modified ............................................................................................................... 669
Reset Input Timing............................................................................................... 671
Interrupt Signal Input Timing............................................................................... 671
IRQOUT Timing .................................................................................................. 671
Bus Release Timing.............................................................................................. 672
Pin Drive Timing at Standby................................................................................ 672
Basic Bus Cycle (No Wait) .................................................................................. 675
Basic Bus Cycle (One Wait)................................................................................. 676
Basic Bus Cycle (External Wait, WAITSEL = 1) ................................................ 677
Rev. 5.00, 09/03, page xxxvi of xliv