SH7709S Datasheet, PDF (239/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Standby to Power-On Reset
Oscillation stops Reset
CKIO, CKIO2*⁷
RESETP*¹
STATUS
Normal*⁵
Standby*⁴ _*2
Reset*³
Normal*⁵
0 to 10 Bcyc*⁶
0 to 30 Bcyc*⁶
Notes: 1.
2.
3.
4.
5.
6.
7.
When standby mode is cleared with a power-on reset, the WDT does not
count. Keep RESETP low during the PLL’s oscillation settling time.
Undefined
Reset: HH (STATUS1 high, STATUS0 high)
Standby: LH (STATUS1 low, STATUS0 high)
Normal: LL (STATUS1 low, STATUS0 low)
Bcyc: Bus clock cycle
The CKIO2 output is available only in clock modes 0, 1, and 2.
Figure 8.5 Standby to Power-On Reset STATUS Output
Rev. 5.00, 09/03, page 195 of 760