SH7709S Datasheet, PDF (31/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

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Block Diagram ..................................................................................................... 6
Pin Assignment (FP-208C, FP-208E) .................................................................. 7
Pin Assignment (BP-240A).................................................................................. 8
User Mode Register Configuration ...................................................................... 20
Privileged Mode Register Configuration.............................................................. 21
General Registers ................................................................................................. 22
System Registers .................................................................................................. 23
Register Set Overview, Control Registers ............................................................ 24
Longword ............................................................................................................. 25
Data Format in Memory ....................................................................................... 25
Processor State Transitions................................................................................... 54
MMU Functions ................................................................................................... 57
Virtual Address Space Mapping........................................................................... 59
MMU Register Contents ...................................................................................... 62
Overall Configuration of the TLB ........................................................................ 63
Virtual Address and TLB Structure...................................................................... 64
TLB Indexing (IX = 1) ......................................................................................... 65
TLB Indexing (IX = 0) ......................................................................................... 66
Objects of Address Comparison ........................................................................... 67
Operation of LDTLB Instruction.......................................................................... 71
Synonym Problem ................................................................................................ 73
MMU Exception Generation Flowchart ............................................................... 78
MMU Exception Signals in Instruction Fetch ...................................................... 79
MMU Exception Signals in Data Access ............................................................. 80
Specifying Address and Data for Memory-Mapped TLB Access ........................ 82
Vector Table......................................................................................................... 86
Example of Acceptance Order of General Exceptions ......................................... 89
Bit Configurations of EXPEVT, INTEVT, INTEVT2, and TRA Registers......... 92
Cache Structure .................................................................................................... 104
CCR Register Configuration ................................................................................ 106
CCR2 Register Configuration .............................................................................. 107
Cache Search Scheme (Normal Mode) ................................................................ 110
Write-Back Buffer Configuration......................................................................... 112
Specifying Address and Data for Memory-Mapped Cache Access...................... 114
Block Diagram of INTC....................................................................................... 118
Example of IRL Interrupt Connection.................................................................. 122
Interrupt Operation Flowchart .............................................................................. 144
Example of Pipeline Operations when IRL Interrupt is Accepted ....................... 148
Block Diagram of User Break Controller............................................................. 150
Canceling Standby Mode with STBCR.STBY..................................................... 189
Power-On Reset (Clock Modes 0, 1, 2, and 7) STATUS Output ......................... 192
Rev. 5.00, 09/03, page xxxi of xliv