SH7709S Datasheet, PDF (205/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bits 3 and 2—Read/Write Select B (RWB1, RWB0): Select the read cycle or write cycle as the
bus cycle of the channel B break condition.
Bit 3: RWB1
0
1
Bit 2: RWB0
0
1
0
1
Description
Condition comparison is not performed
(Initial value)
The break condition is the read cycle
The break condition is the write cycle
The break condition is the read cycle or write cycle
Bits 1 and 0—Operand Size Select B (SZB1, SZB0): Select the operand size of the bus cycle for
the channel B break condition.
Bit 1: SZB1
0
1
Bit 0: SZB0
0
1
0
1
Description
The break condition does not include operand size
(Initial value)
The break condition is byte access
The break condition is word access
The break condition is longword access
Rev. 5.00, 09/03, page 161 of 760