SH7709S Datasheet, PDF (543/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Table 15.4 Relationship of n to CKS1 and CKS0
n
CKS1
0
0
1
0
2
1
3
1
CKS0
0
1
0
1
Table 15.5 Examples of Bit Rate B (Bits/s) for SCBRR Settings (n = 0)
Pφ (MHz)
N
7.1424 10.00
10.7136 13.00
14.2848
0
9600.0 13440.9 14400.0 17473.1 19200.0
1
4800.0 6720.4 7200.0 8736.6 9600.0
2
3200.0 4480.3 4800.0 5824.4 6400.0
Note: The bit rate is rounded to one decimal place.
16.00
21505.4
10752.7
7168.5
18.00
24193.5
12096.8
8064.5
Calculate the value to be set in the bit rate register (SCBRR) from the operating frequency and the
bit rate. N is an integer in the range 0 ≤ N ≤ 255, specifying a smallish error.
N
=
1488
Pφ
× 2^2n−1
×
B
×
10⁶
−
1
Table 15.6 Examples of SCBRR Settings for Bit Rate B (Bits/s) (n = 0)
7.1424
N Error
0 0.00
10.00
N Error
1 30.00
φ (MHz) (9600 Bits/s)
10.7136
13.00
14.2848
N Error N Error N Error
1 25.00 1 8.99 1 0.00
16.00
N Error
1 12.01
18.00
N Error
2 15.99
Rev. 5.00, 09/03, page 499 of 760