SH7709S Datasheet, PDF (382/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit 17—Acknowledge Mode Bit (AM): Specifies whether DACK is output in the data read cycle
or in the data write cycle in dual address mode.
DACK is always output in single address mode, regardless of this bit specification.
This bit is only valid in CHCR0 and CHCR1. Writing to this bit is invalid in CHCR2 and
CHCR3; 0 is read if this bit is read. The write value should always be 0.
Bit 17: AM
0
1
Description
DACK output in read cycle
DACK output in write cycle
(Initial value)
Bit 16—Acknowledge Level (AL): Specifies whether DACK (acknowledge) signal output is
active-high or active-low.
This bit is only valid in CHCR0 and CHCR1. Writing to this bit is invalid in CHCR2 and
CHCR3; 0 is read if this bit is read. The write value should always be 0.
Bit 16: AL
0
1
Description
Active-low DACK output
Active-high DACK output
(Initial value)
Bits 15 and 14—Destination Address Mode Bits 1 and 0 (DM1, DM0): Select whether the
DMA destination address is incremented, decremented, or left fixed.
Bit 15: DM1
0
0
1
1
Bit 14: DM0
0
1
0
1
Description
Fixed destination address
(Initial value)
Destination address is incremented (+1 in 8-bit transfer, +2 in
16-bit transfer, +4 in 32-bit transfer, +16 in 16-byte transfer)
Destination address is decremented (–1 in 8-bit transfer, –2 in
16-bit transfer, –4 in 32-bit transfer; illegal setting in 16-byte
transfer)
Setting prohibited
Rev. 5.00, 09/03, page 338 of 760