SH7709S Datasheet, PDF (151/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

31
9 87
21 0
W3 W3
LOAD LOCK
W2 W2
LOAD LOCK
W2LOCK: Way 2 lock bit. W2LOAD: Way 2 load bit.
When W2LOCK = 1 & W2LOAD = 1 & SR, CL = 1, the prefetched data will always be
loaded into Way2. In all other conditions the prefetched data will be loaded into the way
pointed by LRU.
W3LOCK: Way 3 lock bit. W3LOAD: Way 3 load bit.
When W3LOCK = 1 & W3LOAD = 1 & SR, CL = 1, the prefetched data will always be
loaded into Way3. In all other conditions the prefetched data will be loaded into the way
pointed by LRU.
Note: W2LOAD and W3LOAD should not be set to high at the same time.
—: Reserved bits.
Figure 5.3 CCR2 Register Configuration
Whenever CCR2 bit 8 (W3LOCK) or bit 0 (W2LOCK) is high the cache is locked. The locked
data will not be overwritten unless W3LOCK bit and W2LOCK bit are reset or the PREF
condition during DSP mode matched. During cache locking mode, the LRU in table 5.2 will be
replaced by tables 5.4 to 5.8.
Table 5.4 Way Replacement when PREF Instruction Ended Up in a Cache Miss
DSP bit W3LOAD W3LOCK W2LOAD
0
*
*
*
1
*
0
*
1
*
0
0
1
0
1
*
1
0
1
0
1
0
*
1
1
1
1
0
*: Don't care
Do not set as W3LOAD=1 and also W2LOAD=1
W2LOCK
*
0
1
0
1
1
*
Way to be replaced
Depends on LRU (table 5.2)
Depends on LRU (table 5.2)
Depends on LRU (table 5.6)
Depends on LRU (table 5.7)
Depends on LRU (table 5.8)
Way 2
Way 3
Rev. 5.00, 09/03, page 107 of 760