SH7709S Datasheet, PDF (20/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Section 7 User Break Controller...................................................................................... 149
7.1 Overview ........................................................................................................................... 149
7.1.1 Features ................................................................................................................ 149
7.1.2 Block Diagram ..................................................................................................... 150
7.1.3 Register Configuration ......................................................................................... 151
7.2 Register Descriptions......................................................................................................... 152
7.2.1 Break Address Register A (BARA)...................................................................... 152
7.2.2 Break Address Mask Register A (BAMRA) ........................................................ 153
7.2.3 Break Bus Cycle Register A (BBRA) .................................................................. 154
7.2.4 Break Address Register B (BARB) ...................................................................... 156
7.2.5 Break Address Mask Register B (BAMRB)......................................................... 157
7.2.6 Break Data Register B (BDRB) ........................................................................... 158
7.2.7 Break Data Mask Register B (BDMRB) .............................................................. 159
7.2.8 Break Bus Cycle Register B (BBRB)................................................................... 160
7.2.9 Break Control Register (BRCR)........................................................................... 162
7.2.10 Execution Times Break Register (BETR) ............................................................ 166
7.2.11 Branch Source Register (BRSR) .......................................................................... 167
7.2.12 Branch Destination Register (BRDR) .................................................................. 168
7.2.13 Break ASID Register A (BASRA) ....................................................................... 169
7.2.14 Break ASID Register B (BASRB) ....................................................................... 169
7.3 Operation Description ....................................................................................................... 170
7.3.1 Flow of the User Break Operation........................................................................ 170
7.3.2 Break on Instruction Fetch Cycle ......................................................................... 170
7.3.3 Break by Data Access Cycle ................................................................................ 171
7.3.4 Sequential Break .................................................................................................. 172
7.3.5 Value of Saved Program Counter......................................................................... 172
7.3.6 PC Trace............................................................................................................... 173
7.3.7 Usage Examples ................................................................................................... 174
7.3.8 Notes .................................................................................................................... 179
Section 8 Power-Down Modes......................................................................................... 181
8.1 Overview ........................................................................................................................... 181
8.1.1 Power-Down Modes............................................................................................. 181
8.1.2 Pin Configuration ................................................................................................. 183
8.1.3 Register Configuration ......................................................................................... 183
8.2 Register Descriptions......................................................................................................... 183
8.2.1 Standby Control Register (STBCR) ..................................................................... 183
8.2.2 Standby Control Register 2 (STBCR2) ................................................................ 185
8.3 Sleep Mode........................................................................................................................ 187
8.3.1 Transition to Sleep Mode ..................................................................................... 187
8.3.2 Canceling Sleep Mode.......................................................................................... 187
8.3.3 Precautions when Using the Sleep Mode ............................................................. 187
8.4 Standby Mode.................................................................................................................... 188
Rev. 5.00, 09/03, page xx of xliv