SH7709S Datasheet, PDF (572/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Table 16.3 SCSMR Settings
n
Clock Source
CKS1
0
Pφ
0
1
Pφ/4
0
2
Pφ/16
1
3
Pφ/64
1
Note: The bit rate error is given by the following formula:
Error (%) =
Pφ
(N+1) × 64 × 2^2n−1 × B
× 10⁶ − 1
SCSMR Settings
CKS0
0
1
0
1
× 100
Table 16.4 lists examples of SCBRR settings.
Table 16.4 Bit Rates and SCBRR Settings
Bit Rate (bits/s) n
110
1
150
1
300
0
600
0
1200
0
2400
0
4800
0
9600
0
19200
0
31250
0
38400
0
2
N
Error (%) n
141 0.03
1
103 0.16
1
207 0.16
0
103 0.16
0
51
0.16
0
25
0.16
0
12
0.16
0
6
–6.99 0
2
8.51
0
1
0.00
0
1
–18.62 0
Pφ (MHz)
2.097152
N
Error (%) n
148 –0.04 1
108 0.21
1
217 0.21
0
108 0.21
0
54
–0.70 0
26
1.14
0
13
–2.48 0
6
–2.48 0
2
13.78 0
1
4.86
0
0
–14.67 0
2.4576
N
Error (%)
174 –0.26
127 0.00
255 0.00
127 0.00
63 0.00
31 0.00
15 0.00
7
0.00
3
0.00
1
22.88
1
0.00
Rev. 5.00, 09/03, page 528 of 760