SH7709S Datasheet, PDF (546/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Initialization
Clear TE and RE bits in SCSCR to 0 (1)
Clear FER/ERS, PER
(2)
and ORER flags in SCSSR to 0
Set parity in O/E bit,
set clock in CKS1 and CKS0 bits, ⁽³⁾
and set C/A, in SCSMR
Set SMIF, SDIR,
and SINV bits in SCSMR
(4)
Set value in SCBRR
(5)
Set clock in CKE1 and CKE0 bits,
and clear TIE, RIE, TE, RE, MPIE, (6)
and TEIE bits to 0, in SCSCR
Wait
Has a 1-bit
No
interval elapsed?
Yes
Set TIE, RIE, TE, and RE bits
in SCSCR
(7)
End
Note: Numbers in parentheses refer to steps in the preceding procedure description.
Figure 15.5 Initialization Flowchart (Example)
Rev. 5.00, 09/03, page 502 of 760