SH7709S Datasheet, PDF (663/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit 5—A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 during
A/D conversion. It can also be set to 1 by external trigger input at the ADTRG pin.
Bit 5: ADST
0
1
Description
A/D conversion is stopped
(Initial value)
(1) Single mode: A/D conversion starts; ADST is automatically cleared to 0 when
conversion ends
(2) Multi mode: A/D conversion starts; ADST is automatically cleared to 0 when
conversion ends on all selected channels
(3) Scan mode: A/D conversion starts and continues, cycling through the selected
channels, until ADST is cleared to 0 by software, by a reset, or by a transition
to standby mode
Bit 4—Multi Mode (MULTI): Selects single mode, multi mode or scan mode. For further
information on operation in these modes, see section 20.4, Operation.
Bit 4: MULTI
0
1
ADCR: Bit5: SCN Description
0
Single mode
1
0
Multi mode
1
Scan mode
(Initial value)
Bit 3—Clock Select (CKS): Selects the A/D conversion time. Clear the ADST bit to 0 before
changing the conversion time.
Bit 3:CKS
0
1
Description
Conversion time = 536 states (maximum)
Conversion time = 266 states (maximum)
(Initial value)
Rev. 5.00, 09/03, page 619 of 760