SH7709S Datasheet, PDF (179/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bits 5 and 4—IRQ2 Sense Select (IRQ21S, IRQ20S): Select whether the interrupt signal to the
IRQ2 pin is detected at the rising edge, at the falling edge, or at the low level.
Bit 5: IRQ21S
0
1
Bit 4: IRQ20S
0
1
0
1
Description
An interrupt request is detected at IRQ2 input falling edge
(Initial value)
An interrupt request is detected at IRQ2 input rising edge
An interrupt request is detected at IRQ2 input low level
Reserved
Bits 3 and 2—IRQ1 Sense Select (IRQ11S, IRQ10S): Select whether the interrupt signal to the
IRQ1 pin is detected at the rising edge, at the falling edge, or at the low level.
Bit 3: IRQ11S
0
1
Bit 2: IRQ10S
0
1
0
1
Description
An interrupt request is detected at IRQ1 input falling edge
(Initial value)
An interrupt request is detected at IRQ1 input rising edge
An interrupt request is detected at IRQ1 input low level
Reserved
Bits 1 and 0—IRQ0 Sense Select (IRQ01S, IRQ00S): Select whether the interrupt signal to the
IRQ0 pin is detected at the rising edge, at the falling edge, or at the low level.
Bit 1: IRQ01S
0
1
Bit 0: IRQ00S
0
1
0
1
Description
An interrupt request is detected at IRQ0 input falling edge
(Initial value)
An interrupt request is detected at IRQ0 input rising edge
An interrupt request is detected at IRQ0 input low level
Reserved
Rev. 5.00, 09/03, page 135 of 760