SH7709S Datasheet, PDF (129/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Section 4 Exception Handling
4.1 Overview
4.1.1 Features
Exception handling is separate from normal program processing, and is performed by a routine
separate from the normal program. In response to an exception handling request due to abnormal
termination of the executing instruction, control is passed to a user-written exception handler.
However, in response to an interrupt request, normal program execution continues until the end of
the executing instruction. Here, all exceptions other than resets and interrupts will be called
general exceptions. There are thus three types of exceptions: resets, general exceptions, and
interrupts.
4.1.2 Register Configuration
Table 4.1 lists the registers used for exception handling. A register with an undefined initial value
should be initialized by software.
Table 4.1 Register Configuration
Register
Abbr. R/W Size
Initial Value
Address
TRAPA exception register TRA
R/W Longword Undefined
H'FFFFFFD0
Exception event register
EXPEVT R/W Longword Power-on reset: H'000 H'FFFFFFD4
Manual reset: H'020^*1
Interrupt event register
INTEVT R/W Longword Undefined
H'FFFFFFD8
Interrupt event register2 INTEVT2 R Longword Undefined
H'04000000
(H'A4000000)^*2
Notes: 1. H'000 is set in a power-on reset, and H'020 in a manual reset.
2. When address translation by the MMU does not apply, the address in parentheses
should be used.
4.2 Exception Handling Function
4.2.1 Exception Handling Flow
In exception handling, the contents of the program counter (PC) and status register (SR) are saved
in the saved program counter (SPC) and saved status register (SSR), respectively, and execution of
the exception handler is invoked from a vector address. The return from exception handler (RTE)
instruction is issued by the exception handler routine on completion of the routine, restoring the
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