SH7709S Datasheet, PDF (194/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

7.1.2 Block Diagram
Figure 7.1 shows a block diagram of the UBC.
Access
Control
IAB LAB
Access
comparator
Address
comparator
ASID
comparator
Channel A
BBRA
BARA
BAMRA
BASRA
MDB
Access
comparator
Address
comparator
ASID
comparator
Data
comparator
Channel B
PC Trace
CONTROL
BBRB
BARB
BAMRB
BASRB
BDRB
BDMRB
BETR
BRSR
BRDR
BRCR
LDB/IDB/
XDB/YDB
CPU state
signals
User break request
UBC Location
CCN Location
Legend
BBRA:
BARA:
BAMRA:
BASRA:
BBRB:
BARB:
BAMRB:
Break bus cycle register A
Break address register A
Break address mask register A
Break ASID register A
Break bus cycle register B
Break address register B
Break address mask register B
BASRB:
BDRB:
BDMRB:
BETR:
BRSR:
BRDR:
BRCR:
Break ASID register B
Break data register B
Break data mask register B
Break execution times register
Branch source register
Branch destination register
Break control register
Figure 7.1 Block Diagram of User Break Controller
Rev. 5.00, 09/03, page 150 of 760