SH7052 Datasheet, PDF (9/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Page Item
Revisions (See Manual for Details)
562 16.1.3 Pin Configuration
Description amended
570 16.2.3 A/D Control Registers 0 Description amended
and 1 (ADCR0, ADCR1)
585 16.4.4 External Triggering of Description amended
A/D Converter
600 17.5.3 ROM Area Writes
New description added
701 20.5.5 RAM Emulation Register Description of bits 15 to 4 added
(RAMER)
The write value should always be 0.
713 20.7.3 Erase Mode
Description amended
722 20.10 Note on Flash Memory Description added
Programming/Erasing
763 21.7.3 Erase Mode
Description amended
797 23.3.1 Transition to Hardware Description added
Standby Mode
815 to 24.2 DC Characteristics
819
Table 24.4 DC Characteristics
Description amended
837 24.3.9 HCAN Timing
Table 24.14 HCAN Timing
Description amended
840 24.3.11 AUD Timing
Table 24.16 AUD Timing
Load conditions added
863, Appendix A.1 Address
867
Table A.1 Address
Register abbreviations amended: H’FFFFF466,
H’FFFFF526
881,
884 to
886
A.2 Register States in Reset and Table A.2 Register States in Reset and Power-Down
Power-Down States
States
Description amended
891 Appendix D Package
Dimensions
Figure D.1 Package Dimensions (FP-208A)
Amended