SH7052 Datasheet, PDF (154/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

8.2.4 RAM Emulation Register (RAMER)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
— RAMS RAM2 RAM1 RAM0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R/W R/W R/W R/W
The RAM emulation register (RAMER) is a 16-bit readable/writable register that selects the RAM
area to be used when emulating realtime programming of flash memory.
RAMER is initialized to H'0000 by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset or in software standby mode.
Note: To ensure correct operation of the RAM emulation function, the ROM for which RAM
emulation is performed should not be accessed immediately after this register has been
modified. Operation cannot be guaranteed if such an access is made.
• Bits 15 to 4—Reserved: Only 0 should be written to these bits. Operation cannot be guaranteed
if 1 is written.
• Bit 3—RAM Select (RAMS): Used together with bits 2 to 0 to select or deselect flash memory
emulation by RAM (table 8.6).
When 1 is written to this bit, all flash memory blocks are write/erase-protected.
This bit is ignored in modes with on-chip ROM disabled.
• Bits 2 to 0—RAM Area Specification (RAM2 to RAM0): These bits are used together with the
RAMS bit to designate the flash memory area to be overlapped onto RAM (table 8.6).
128