SH7052 Datasheet, PDF (256/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Timer I/O Control Register 11 (TIOR11)
TIOR11
Bit: 7
6
5
4
3
—
—
— IO11B0 —
Initial value: 0
0
0
0
0
R/W: R
R
R
R/W
R
2
1
0
—
— IO11A0
0
0
0
R/W R/W R/W
TIOR11 specifies whether general registers GR11A and GR11B are used as input capture or
compare-match registers, and also performs edge detection and output value setting.
TIOR11 is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
• Bits 7 to 5—Reserved: These bits always reads 0. The write value should always be 0.
• Bit 4—I/O Control 11B0 (IO11B0): These bits select the general register (GR) function.
Bit 4: IO11B0
0
1
Description
Compare-match is disabled
Ccompare-match is enabled
(Initial value)
• Bits 3 to 1—Reserved: These bits always reads 0. The write value should always be 0.
• Bit 0—I/O Control 11A0 (IO11A0): This bit select the general register (GR) function.
Bit 0: IO11A0
0
1
Description
Compare-match is disabled
Ccompare-match is enabled
(Initial value)
230