SH7052 Datasheet, PDF (406/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Sample Setup Procedure for PWM Timer Operation (Channels 3 to 5 ): An example of the
setup procedure for PWM timer operation (channels 3 to 5 ) is shown in figure 10.59.
1. Set the first-stage counter clock ø' in prescaler register 1 (PSCR1), and select the second-stage
counter clock ø" with the CKSEL bit in the timer control register (TCR). When selecting an
external clock, at the same time select the external clock edge type with the CKEG bit in TCR.
2. Set the port control registers (PxCRH, PxCRL) corresponding to the waveform output port to
ATU output compare-match output. Also set the corresponding bit to 1 in the port IO register
(PxIOR) to specify the output attribute.
3. Set bit T3PWM to T5PWM in the timer mode register (TMDR) to PWM mode. When PWM
mode is set, the timer operates in PWM mode irrespective of the timer I/O control register
(TIOR) contents, and general registers (GR3A to GR3D, GR4A to GR4D, GR5A to GR5D)
can be written to.
4. The GR3A to GR3C, GR4A to GR4C, and GR5A to GR5C ATU general registers are used as
duty registers (DTR), and the GR3D, GR4D, and GR5D ATU general registers as cycle
registers (CYLR). Set the PWM waveform output 0 output timing in DTR, and the PWM
waveform output 1 output timing in CYLR. Also, if necessary, interrupt requests can be sent to
the CPU at the 0/1 output timing by making a setting in the timer interrupt enable register
(TIER).
5. Set the corresponding bit to 1 in the timer start register (TSTR) to start the free-running
counter (TCNT) for the relevant channel.
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