SH7052 Datasheet, PDF (820/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

23.2 Register Descriptions
23.2.1 Standby Control Register (SBYCR)
The standby control register (SBYCR) is an 8-bit readable/writable register that sets the transition
to standby mode, and the port state in standby mode. SBYCR is initialized to H'1F by a power-on
reset.
Bit: 7
6
5
4
3
2
1
0
SSBY HIZ
—
—
—
—
—
—
Initial value: 0
0
0
1
1
1
1
1
R/W: R/W R/W
R
R
R
R
R
R
• Bit 7—Software Standby (SSBY): Specifies transition to software standby mode. The SSBY
bit cannot be set to 1 while the watchdog timer is running (when the timer enable bit (TME) in
the WDT timer control/status register (TCSR) is set to 1). To enter software standby mode,
always halt the WDT by clearing the TME bit to 0, then set the SSBY bit.
Bit 7: SSBY
0
1
Description
Executing SLEEP instruction puts the SH7052F/SH7053F/SH7054F into sleep
mode
(Initial value)
Executing SLEEP instruction puts the SH7052F/SH7053F/SH7054F into
standby mode
• Bit 6—Port High Impedance (HIZ): In software standby mode, this bit selects whether to set
I/O port pins to high impedance or hold the pin state. The HIZ bit cannot be set to 1 when the
TME bit of the WDT timer control/status register (TCSR) is set to 1. When making the I/O
port pin state high impedance, always clear the TME bit to 0 before setting the HIZ bit.
Bit 6: HIZ
0
1
Description
Pin states held in software standby mode
Pins go to high impedance in software standby mode
(Initial value)
• Bit 5—Reserved: This bit always reads 0. The write value should always be 0.
• Bits 4 to 0—Reserved: These bits always read 1. The write value should always be 1.
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